1. Field of the Invention
The present invention relates to the field of electronic circuits. More particularly, this invention relates to a circuit and method for transparently switching between two independent interrupt delivery mechanisms preferably implemented within a multi-processor system.
2. Description of the Prior Art
Fundamental to the performance of any computer system, a processor performs a number of operations including controlling various intermittent "services" requested by peripheral devices coupled to the computer system. These services may include data transmission, data capture or any other data manipulative operations essential to the functionality of the peripheral devices. Two interrupt delivery mechanisms are currently being used for detecting an interrupt request from one of the peripheral devices and for advising the processor that a particular service corresponding to the interrupt request needs to be performed; namely, (i) a Programmable Interrupt Controller ("PIC") interrupt delivery mechanism and (ii) an Advanced Programmable Interrupt Controller ("APIC") interrupt delivery mechanism.
For the last two decades, PICs have been widely used as an interrupt delivery mechanism, usually for uni-processor systems. As shown in FIG. 1, a single host processor 105 operates in conjunction with an arbitrary number "n" of peripheral devices 110a-110n which are either permanently coupled to an I/O bus 115 (e.g., an ISA, EISA or PCI bus) or removably coupled to the I/O bus 115 through printed circuit cards, etc. These peripheral devices 110a-110n are coupled to a PIC 120 through a limited number of interrupt request ("IRQ") lines. As shown, the PIC 120 may have an Intel.RTM. 82C59 architecture which is capable of supporting fourteen (14) interrupt requests from peripheral devices 110a-110n via IRQ.sub.1 and IRQ.sub.3 -IRQ.sub.15 lines 126 and 128-140 as shown. Moreover, the PIC 120 includes a register 145 to determine the current operation priority of the host processor 105 and is programmable through information lines 150 in order to determine which IRQ lines 126 and 128-140 are currently valid and their relative priority.
For example, if one of the peripheral devices (e.g., peripheral device 110a) needs the host processor 105 to perform a service, the peripheral device 110a transmits an interrupt request to the PIC 120 by asserting at least one of its IRQ lines (e.g., IRQ.sub.1 line 126). If the service associated with the interrupt request has a greater priority than the current operation of the host processor 105, the PIC 120 asserts an interrupt "INTR" line 155. This interrupts the host processor 105, forcing the host processor 105 to temporarily transition from its current program to a special interrupt service routine. Supporting a limited number of interrupt requests may have been sufficient for a conventional PIC within the uni-processor system, however, with the advent of multi-processor systems, there exists a need for supporting a greater number of interrupt requests. As a result, approximately four years ago, Intel.RTM. Corporation of Santa Clara, Calif. developed APICs.
Well known to those skilled in the art, the APIC is based on a distributed architecture in which interrupt requests are distributed from an "I/O" APIC, coupled to an interrupt source (e.g., peripheral), to a "local" APIC of an interrupt destination (e.g., microprocessor). It is contemplated that the local and I/O APICs may be implemented onto either a single chip or may be integrated with other system components. These APICs operate as another interrupt delivery mechanism, communicating with each other over a dedicated interrupt controller communications ("ICC") bus, allowing multiple processors to share interrupt service activities with one another. Although many current operating systems have been coded to operate with APICs, there exists a number of prior operating systems which exclusively operate with a PIC. As a result, it is quite common to hard-wire both types of controllers together in order to support both interrupt delivery mechanisms as shown in FIG. 2.
Referring now to FIG. 2, a conventional multi-processor system 200 relies on an interrupt chip set 205 (e.g., an Intel.RTM. 82374EB) to provide multiple interrupt delivery mechanisms. The interrupt chip set 205 comprises a PIC 210 (e.g., Intel.RTM. 82C59) and an I/O APIC 215, both of which are programmable through communication lines 211 and 212, respectively. Selecting whether the PIC 210 or the I/O APIC 215 is responsible for controlling interrupt delivery is performed by writing to particular control registers (not shown) within the interrupt chip set 205.
The PIC 210 is coupled to a limited number of IRQ input lines 220 and a first input of a logic gate 225 (e.g., an AND gate) via a PIC interrupt line 230. Upon monitoring these IRQ interrupt lines 220, if the PIC 210 detects an interrupt request (i.e., asserted. IRQ line), the PIC 210 asserts the PIC interrupt line 230. As a result, the logic gate 225 asserts an interrupt "INTR" line 235, which interrupts a designated one of a plurality of processors 240a-240m ("m" being arbitrary), depending on whether the control line 226, coupled to a second input of the logic gate 225 is asserted.
For the logic gate 225 having an "AND" functionality, it asserts the INTR line 235 if the control line 226 is asserted. This occurs when a predetermined control bit of a control register 227 (i.e., an "interrupt mode configuration" register) is set by an operating system (not shown) of the multi-processor system 200. The control register 227 and its operations are discussed on Page 3-6 of a document entitled "Multiprocessor Specification Version 1.1" recently published by Intel.RTM. Corporation of Santa Clara, Calif. This document is incorporated herein by reference.
Referring still to FIG. 2, the I/O APIC 215 is also coupled to the IRQ input lines 220. If the I/O APIC 215 detects an interrupt request which is not exclusively handled by the PIC 210, the I/O APIC 215 places an interrupt signal onto an ICC bus 250. The ICC bus 250 propagates the interrupt signal into local APICs 245a-245m implemented within each of the plurality of processors 240a-240m, respectively.
Thus, for those interrupt requests handled exclusively by the PIC 210, the operating system sets the control bit causing the assertion of the control signal input into the second input of the logic gate 225. This enables the PIC 210 to assert the INTR line 235. Such interrupt requests may include, but are not limited to, initialization of the multi-processor system by its Basic Input/Output Subsystem ("BIOS"), various instructions from older operating systems such as DOS.TM., Windows.TM. 3.1, Windows.TM. 95 and the like. Otherwise, the operating system clears the control bit which de-asserts the control signal input into the second input of the logic gate 225. This directs the I/O APIC 215 to deliver interrupts to the processors 240a-240m. This embodiment, however, offers many disadvantages.
One disadvantage is that this embodiment provides a non-scalable architecture in that it is incapable of providing interrupt services for more than approximately fourteen interrupt requests. More specifically, this embodiment offers no support for the inclusion of additional I/O APICs within the computer system to service more types of interrupts.
Hence, it would be desirable to provide a circuit and method for enabling a computer system to appropriately switch between an interrupt delivery mechanism controlled by the conventional PIC and an interrupt delivery mechanism controlled by at least one additional I/O APIC. Additionally, it would be advantageous to perform such switching in a transparent fashion so that no special instructions are required in the operating system other than those instructions required to support typical PIC and/or APIC operations.